1. Field of the Invention
The present invention relates to direct memory access (DMA) controllers for directly transferring data between memory and input/output (I/O) devices without using any central processing unit (CPU) in an information processor.
2. Description of the Prior Art
In general, it is a waste of time to output data to an I/O device from memory by means of a CPU. One of the fast ways to output data to an I/O device from memory is to directly output data to an I/O device from the data bus. Such DMA requires some hardware, which is called "DMA controller," for supplying addresses and control signals for transferring data to read or write in the memory or I/O device. Like the CPU, the DMA controller generates addresses to read or write in the memory and sends various control signals to the I/O device.
FIG. 3 shows a conventional DMA control system which includes an information processing unit 1 such as a CPU of an electronic computer; a random access memory (RAM) 2; a 4-channel address output device 3; four I/O devices 12; a bus access controller 14; data, address, and control buses 4, 5, and 6 for interconnecting the CPU 1, the address output device 3 the RAM, and the I/O device 12; and a DMA controller 7. The RAM 2 is a dynamic RAM which requires periodic refreshing. Four channels are assigned to the I/O devices 12 corresponding to the channels 0-3 of the address output device 3. The DMA controller 7 includes a transfer counter 9, a request signal generator 10, and a transfer pulse generator 11. The request signal generator 10 is composed of flip-flops such as bistable multivibrators.
The operation will be described with reference to FIG. 4. First of all, one of the I/O devices generates a DMA request signal DRQ (No. 1) for data transfer with the RAM 2. This is a negative logic signal and is represented by DRQ. When the waveform of the request signal DRQ is shaped in the transfer pulse generator 11 and applied to the request signal generator 10, the request signal generator 10 outputs a positive logic bus request signal BRQ to the bus access controller 14. If there is neither DRAM refresh request r with high interrupt priority nor external HOLD request, the bus access controller 14 sends bus available signals BAK-A and inverted BAK-B to the DMA controller 7 and the CPU 1, respectively. That is, upon reception of the request signal BRQ, it generates a bus available signal BAK, the duration of which is determined by the machine cycle. The CPU 1 then cuts off the data bus 4, the address bus 5, and the control bus 6 to stop the use of data from the RAM 2. The DMA controller 7, on the other hand, outputs to the address output device 3 an acknowledge signal DAK indicating that the buses 4-6 are available. The requesting I/O device 12 identified by the address output device 3 then starts DMA transfer with the RAM 2 via the buses 4, 5, and 6.
If the bus available signal BAK is kept to be L, the DMA transfer is carried out in the burst mode. However, since L of the signal BAK is applied to the reset (R) of the request signal generator 10, the signal BAK becomes H at the end of a machine cycle, and the bus request signal BRQ from the request signal generator 10 is inverted to L. Consequently, it cancels the bus available signal BAK and outputs a H signal immediately after one machine cycle which is inherent to the system. Thus, the operation enters a cycle steal mode in which one byte of data is transferred in the machine cycle. When a DMA request signal DRQ is outputted from the channel No. 0 of the I/O device after the bus use permit is transferred to the CPU 1, one byte of data is transferred in the same way as described above.
When a refresh request r is inputted during the DMA transfer, the DMA controller 7 stops while the address output device 3 releases the buses 4, 5, and 6 for refreshing and resumes DMA transfer when the memory refresh is completed.
However, the conventional DMA controller requires a preparation period t necessary for the initial setting to effect data transfer within the period T in which the address output device 3 is given a bus use permit. Since this preparation period t is necessary for each transfer of one byte, the effective data transfer time is (T-t), resulting in the low bus efficiency. Thus, there is a waste of time on the bus for data transfer in the cycle steal mode.